The new GitHub repo schlae/IBM_MCGA releases a complete reverse‑engineered dump of IBM’s MCGA video chipset. MCGA powered the PS/2 Model 25 and 30 as a low‑cost solution. The design splits into a memory‑controller gate array and a video‑formatter gate array, with certain dies produced on IBM’s internal line and others on Seiko SLA parts.

The memory controller 72X8300 uses a Seiko SLA6430 array with 4,342 basic cells on a 2 µm CMOS process and two metal layers. The video formatter 72X8205 employs a SLA6330 array of 3,312 cells. Engineers found a genlock mode that routes HSYNC and VSYNC to pins 11/12, enabled by writing 1 to bit 3 of register 0x12, despite the spec marking the bit reserved.

The author reduced the original 21,808 × 21,778 pixel die images, imported them into KiCAD at a 0.103 scale and built footprints for each basic cell linked to schematic symbols. Power runs on metal‑2 columns, signals on metal‑1, enabling netlist extraction. Future work will export Verilog, delivering a usable model for emulators.