AMD's upcoming MI400 series accelerators revealed via LLVM commits show two new chips: GFX1250 (MI455X) for ML powering Helios rack, and GFX1251 (MI430X) for HPC projecting over 200 TFLOPs double-precision. GFX1250 uses WGP architecture with four SIMDs per CU, shared vector L0 cache, and operates only in Wave32 mode with 20 waves per SIMD.

Major register file upgrade: each wave can address up to 1024 VGPRs, doubling CDNA's 512 and quadrupling RDNA's 256. LDS increased to 320KB per wavefront, with LDS and vector L0 merged into a single 448KB WGP Cache. GFX1250 retains packed fp32 ops and CDNA's SDMA units but strips all graphics features (no rasterizer, texture, ray tracing, buffer instructions).

Tensor capabilities combine RDNA4's WMMA programming model with CDNA4's performance. GFX1250 supports M=N=16 with K=4/32/64/128 for various precisions, plus OCP MX scaling. New LDS transpose instructions and thread block cluster-like scheduling hint at future consumer GPU features.