The author has been developing floss, an AArch64 operating system kernel targeting QEMU and Raspberry Pi boards. Testing on real hardware revealed issues not caught by QEMU emulation. This post details implementing a spin lock using load exclusive (ldaxr) and store exclusive (stxr) instructions for mutual exclusion between CPU cores.
The lock uses a 32-bit word where 0 means unlocked and 1 means locked. The ldaxr instruction includes acquire semantics to prevent memory reordering, while stlr (store-release) in unlock ensures release semantics. The implementation guards against core output interleaving, ensuring only one core prints at a time.
However, real hardware occasionally causes exceptions during load exclusive operations that QEMU doesn't emulate. The author validates correctness through testing, noting the basic spin lock lacks fairness and has poor performance due to busy-waiting, suggesting future work on wfe/sev for power-efficient waiting.
Source: Hacker News · Summarized by HeadlinesBriefing