Talos represents a fundamental rethinking of deep learning inference, implementing a complete CNN pipeline directly in SystemVerilog on FPGA hardware. Unlike flexible software frameworks designed for training, Talos strips away runtime overhead, schedulers, and operating systems to expose raw compute capability at the circuit level. This approach enables deterministic, cycle-accurate control over every calculation, maximizing efficiency for production inference scenarios where response time dominates performance requirements.

The hardware implements a Q16.16 fixed-point arithmetic system instead of floating-point numbers, with 32-bit values where upper bits represent integers and lower bits represent fractions. Each operation follows precise hardware constraints - convolution becomes multiply-accumulate loops, max-pool and ReLU are fused for efficiency, and streaming pipelines avoid intermediate buffering. Developers face brutal debugging challenges when timing misses occur by even half a nanosecond, requiring hours of waveform analysis to identify single-bit errors.

Talos prioritizes specialized efficiency over generality, accepting FPGA constraints of fixed logic elements, memory, and clock budgets. The documented implementation handles a 28×28 grayscale input through convolution, ReLU, max-pool, and fully connected layers, mapping directly to 10 output classes. By removing