A case study of the B200 pipeline model reveals critical instruction scheduling hazards. Based on microbenchmarks executed directly on B200 silicon, the analysis shows that static analysis is insufficient for validating instruction schedules on deep-pipeline GPUs. The hardware pipeline is the final arbiter of correctness; under-stalling dependencies allows consumer instructions to read stale register state, causing silent miscomputation without exceptions.

The most elusive bug involved a predicate-consumer under-stall. An ISET P instruction writing predicate P1 was followed by a BRA instruction reading P1. The scheduler missed the RAW dependency, inserting only 4 cycles of delay against a modeled 13 cycles latency. The branch read stale state (0 instead of 1), took the wrong execution edge, and caused silent failure. On-silicon probing revealed the actual predicate latency floor sits at approximately 4 cycles.

Fixed-latency arithmetic instructions also exhibit precise hazards. FFMA (FP32) requires a 4 cycles stall floor, while DFMA (FP64) requires 8 cycles — exactly twice the latency. Validation requires floating-point recurrence chains, as integer chains can be masked by hardware forwarding networks. The defense combines rigorous operand analysis with dynamic on-device latency probing.