Auto-arch-tournament, a system developed by FeSens, autonomously optimized an in-order RISC-V CPU core, achieving 92% performance gains over the original VexRiscv baseline. The project used a closed-loop research framework where an LLM proposed microarchitectural changes, implemented them in SystemVerilog, and validated via formal verification, RTL synthesis, and FPGA benchmarks. After 9.5 hours of experimentation, the agent generated 10 accepted improvements, including innovations like a cold multi-cycle DIV/REM unit and a registered lookahead I-fetch replay predictor. These modifications boosted CoreMark iter/cycle from 301 to 577 and increased Fmax frequency to 199 MHz, outperforming human-tuned configurations.

The system’s rigorous verification pipeline prevented flawed implementations from reaching hardware. Each hypothesis underwent 53 symbolic formal checks, RTL cosimulation, and CRC validation against canonical benchmarks. Failures included path sandboxes blocking unauthorized file edits and a 73% fitness drop from a misconfigured predictor. The agent learned from these errors, iterating toward stable, high-performance designs.

By locking the baseline at VexRiscv’s original parameters, the experiment isolated the agent’s impact. Unlike traditional CPU development, which took years to reach similar milestones, the loop closed 13 performance gaps in 10 hours. The results highlight the potential of AI-driven architecture tuning but emphasize that domain-specific verification remains irreplaceable. The project’s open-source code and methodology provide a blueprint for future engineering workflows.

This work underscores a shift in hardware development: while autonomous loops handle optimization, human expertise in defining correctness criteria remains critical. The auto-arch-tournament framework demonstrates how AI can accelerate low-level design exploration, though real-world deployment will require tighter integration with formal methods and domain knowledge.