Welcome to the first feature article on our site. We’re going to cover an ongoing problem with x86 emulation that affects every application that we emulate. This comes down to a single over-arching term that has wide-reaching ramifications; Emulating the x86 Total Store Ordering memory model (x86-TSO). The problems with emulating this memory model on the weak ordering memory model that ARM defines is multi-faceted and covers multiple issues. We’re going to go over all the problems that we can encounter and the ways we solve (or in some cases can’t solve) in this article.

What exactly is x86-TSO? A memory model is a set of rules for how memory accesses in a system behave in relation to each other. The rules dictate how loads and stores interact in a single-threaded or multi-threaded environment. The two we care about today are ARM’s relaxed (or weak) consistency model, and the x86 variant of Total-Store-Ordering consistency model. These two models are basically the two extremes of the spectrum; where ARM is the most relaxed, allowing significant hardware optimizations; and x86 is the most strict, enforcing a very strong coherency model.

With TSO being very strict, the programmer can assume that when a memory store occurs, it will be coherently visible to all other processors. The weak memory model that ARM has is less intuitive. By default, regular memory loads and stores aren’t strictly coherent across processors, allowing the CPU to operate more efficiently. ARM introduced load-acquire and store-release memory instructions to address consistency, mapping to C++ std::atomic’s memory_order_acquire and memory_order_release.