The Voyager Flight Data Subsystem (FDS) Emulator replicates the original 1977 hardware used on Mariner‑Jupiter‑Saturn missions. Running at 806.4 k Hz it can execute ~400,000 instructions per second and reproduces the 8 K × 16‑bit CMOS memory layout used aboard Voyager 1, now 24 596 234 112 km from Earth with a one‑way delay of 22 h 51 m.

Its instruction set includes load, store, arithmetic, logical, jump, skip, halt, and word‑define operations. The CPU clock of 806.4 k Hz yields a cycle time of 2.48 µs, while a 2.5 ms interrupt period allows periodic error‑recovery routines. Word size is 16‑bit with 12‑bit addresses and a 4‑bit opcode.

Memory is split into two 4 K banks of 16‑bit CMOS RAM, with registers RA, RB and 128 working registers plus special registers. Serial I/O supports 32‑bit input and 16‑bit output, and four DMA channels (MDS, DSS, ISS, PRA) operate at 115.2 kbps.

Documentation lives in the JPL archive, scanned between 1974‑1977 and preserved by Wichita State University Special Collections. The emulator allows researchers to study legacy spacecraft software in a modern environment.