Assembly Hall of Shame takes the opposite approach to performance optimization: searching for the absolute floor of single-instruction performance. Instead of making code run fast, it finds the slowest possible way to execute one instruction.

The current champion is fxrstor64, which loads 512-byte FPU/MMX/XMM state from a high-latency MMIO region in the PCIe fabric. By starving the fabric with hammer cores, the instruction queues behind contending traffic. On an AMD Ryzen 7 5800H, it scored 198,002,498,236 cycles (62 seconds).

The leaderboard includes tricks like using subnormal divisors to trigger FP assists, saturating write-combining buffers with `mfence`, and exploiting split locks. Notable entries: `nop` scores 1 cycle, `rdtsc` 49 cycles, `idiv` 77 cycles, and `cpuid` 1,248 cycles. The Intel Core i7-8559U dominates many entries, while VIA's undocumented MSR hits 161,602 cycles.

Rules require a single instruction, no interrupts, and factory stock hardware. The project highlights how microcode assists, memory fabric contention, and device quirks can drastically inflate instruction latency.